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Hierarchical Modeling for VLSI Circuit Testing - The Springer International Series in Engineering and Computer Science 1990 edition
Debashis Bhattacharya
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Hierarchical Modeling for VLSI Circuit Testing - The Springer International Series in Engineering and Computer Science 1990 edition
Debashis Bhattacharya
To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.
160 pages, biography
| Medios de comunicación | Libros Hardcover Book (Libro con lomo y cubierta duros) |
| Publicado | 31 de diciembre de 1989 |
| ISBN13 | 9780792390589 |
| Editores | Springer |
| Páginas | 160 |
| Dimensiones | 155 × 235 × 11 mm · 426 g |
| Lengua | English |
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