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ASIC Design and Synthesis: RTL Design Using Verilog Vaibbhav Taraate 2021 edition
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ASIC Design and Synthesis: RTL Design Using Verilog
Vaibbhav Taraate
This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
330 pages, 184 Illustrations, color; 127 Illustrations, black and white; XXI, 330 p. 311 illus., 184
| Medios de comunicación | Libros Paperback Book (Libro con tapa blanda y lomo encolado) |
| Publicado | 8 de enero de 2022 |
| ISBN13 | 9789813346444 |
| Editores | Springer Verlag, Singapore |
| Páginas | 330 |
| Dimensiones | 150 × 220 × 10 mm · 494 g |
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